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R1EX25512ASA00A/R1EX25512ATA00A
Read Status Register (RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at
any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is
recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously, as shown in the following figure.
Read Status Register (RDSR) Sequence
S
W
V IH
V IL
V IH
V IL
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
C
D
V IH
V IL
V IH
V IL
Status Register Out
Q
High-Z
7
6
5
4
3
2
1
0
7
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register
cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1, the
internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write or Write Status
Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software
protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When
one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as defined in the Write Protect
Block Size table) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be
written provided that the Hardware Protected mode has not been set.
SRWD bit: The Status Register Write Disable (SRWD) bit is operated in conjunction with the write protect ( W ) signal.
The Status Register Write Disable (SRWD) bit and write protect ( W ) signal allows the device to be put in the Hardware
Protected mode (When the Status Register Write Disable (SRWD) bit is set to 1, and write protect ( W ) signal is driven
low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write
Status Register (WRSR) instruction is no longer accepted for execution.
R10DS0046EJ0200 Rev.2.00
Oct.04, 2010
Page 12 of 20
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